~ruther/verilog-riscv-semestral-project

ref: ca9604e2c8a9c44ccba5223ef095d84cd618bbe1 verilog-riscv-semestral-project/Makefile -rwxr-xr-x 1.4 KiB
707b5bfc — Rutherther 2 years ago 
chore: add makefile for both verilog and c