~ruther/verilog-riscv-semestral-project: Makefile 707b5bfcbb7652d77af7da28688aceff0a98892b

~ruther/verilog-riscv-semestral-project

ref: 707b5bfcbb7652d77af7da28688aceff0a98892b verilog-riscv-semestral-project/Makefile -rwxr-xr-x 1.4 KiB

707b5bfc — Rutherther 1 year, 5 months ago

chore: add makefile for both verilog and c