~ruther/verilog-riscv-semestral-project: programs/start.S c682cc068ee41da1b00fbd51dfb79f9cd5560d0d

~ruther/verilog-riscv-semestral-project

ref: c682cc068ee41da1b00fbd51dfb79f9cd5560d0d verilog-riscv-semestral-project/programs/start.S -rwxr-xr-x 95 bytes

a400aceb — Rutherther 2 years ago

feat: make RAM word aligned, add byte_enable

Support sb, sh, lb, lh using byte enable
instead of non-word aligned reads and writes.

30a7f949 — Rutherther 2 years ago

feat: add basic testing programs