~ruther/verilog-riscv-semestral-project: tests/official/env c5e322db080e580a25dafe64d29405db34adec57

~ruther/verilog-riscv-semestral-project

ref: c5e322db080e580a25dafe64d29405db34adec57 verilog-riscv-semestral-project/tests/official/env d---------

308a1462 — Rutherther 3 years ago

tests: add register dump, printing

51842d38 — Rutherther 3 years ago

feat: add support for official tests