~ruther/verilog-riscv-semestral-project

ref: c5e322db080e580a25dafe64d29405db34adec57 / d---------
c5e322db — Rutherther fix: use reg for procedural assignments 1 year, 4 months ago
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.envrc
10 bytes
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.gitignore
110 bytes
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.gitmodules
137 bytes
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Makefile
2.5 KiB
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README.md
2.8 KiB
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flake.lock
1.5 KiB
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flake.nix
1.1 KiB
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programs/
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src/
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testbench/
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tests/
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