~ruther/verilog-riscv-semestral-project: src/ram.sv bc02aba5f50d84e93657a0601f713d990ecb8f11

~ruther/verilog-riscv-semestral-project

ref: bc02aba5f50d84e93657a0601f713d990ecb8f11 verilog-riscv-semestral-project/src/ram.sv -rwxr-xr-x 221 bytes

8adc02d7 — Rutherther 2 years ago

feat: add basic ram, alu, and register file