~ruther/verilog-riscv-semestral-project

ref: b89bec430c94042ce0fce7527aad91a42af9f00b verilog-riscv-semestral-project/src/ram.sv -rwxr-xr-x 1.1 KiB
df876b38 — Rutherther 2 years ago
chore: extend memory
308a1462 — Rutherther 2 years ago
tests: add register dump, printing
32388b78 — Rutherther 2 years ago
feat: add support for loading and saving ram from disk
a400aceb — Rutherther 2 years ago
feat: make RAM word aligned, add byte_enable

Support sb, sh, lb, lh using byte enable
instead of non-word aligned reads and writes.
ca9604e2 — Rutherther 2 years ago
fix: offset ram by bytes, not bits
acf0f724 — Rutherther 2 years ago
feat: implement sb, sh, lb, lh support via masking
8adc02d7 — Rutherther 2 years ago
feat: add basic ram, alu, and register file