~ruther/verilog-riscv-semestral-project

ref: b0f8702877121832dfdee7d921af417237673284 verilog-riscv-semestral-project/src/file_program_memory.sv -rwxr-xr-x 319 bytes
308a1462 — Rutherther 2 years ago
tests: add register dump, printing
51842d38 — Rutherther 2 years ago
feat: add support for official tests
ee0204c8 — Rutherther 2 years ago
feat: pass program to execute by parameter
938d89a2 — Rutherther 2 years ago
refactor: change program mem to file prog mem
64d33d25 — Rutherther 2 years ago
feat: add program memory