~ruther/verilog-riscv-semestral-project

ref: af6386a7cb0eb3b58cd754956dca300d416cbcde verilog-riscv-semestral-project/src/stages/decode.sv -rw-r--r-- 2.9 KiB 
fix: jumping should flush two registers

feat: move jumping to execute stage

Merge pull request #1 from Rutherther/feat/pipeline

Implement pipeline
docs: better document the stage code, organize it better

feat: add forwarding signal for better debugging

feat: implement pipeline
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