~ruther/verilog-riscv-semestral-project: tests/official/env a6f4c7fc1c66f05cd78d52e8e3b9229ae58ef2f7

~ruther/verilog-riscv-semestral-project

ref: a6f4c7fc1c66f05cd78d52e8e3b9229ae58ef2f7 verilog-riscv-semestral-project/tests/official/env d---------

308a1462 — Rutherther 2 years ago

tests: add register dump, printing

51842d38 — Rutherther 2 years ago

feat: add support for official tests