~ruther/verilog-riscv-semestral-project

ref: a6f4c7fc1c66f05cd78d52e8e3b9229ae58ef2f7 verilog-riscv-semestral-project/src/cpu_types.sv -rwxr-xr-x 1.8 KiB 
feat: implement pipeline

feat: implement sb, sh, lb, lh support via masking

chore: add cpu types for various sources

Better orientation by name instead of
number
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