~ruther/verilog-riscv-semestral-project

ref: a6f4c7fc1c66f05cd78d52e8e3b9229ae58ef2f7 verilog-riscv-semestral-project/programs/branches.c -rwxr-xr-x 780 bytes
tests: add more custom tests
feat: store c results in memory addr 0
feat: add branches.c test
Do not follow this link