~ruther/verilog-riscv-semestral-project

ref: a400aceb574400fad6b269927793a5c13aab647c verilog-riscv-semestral-project/testbench d--------- 
feat: make RAM word aligned, add byte_enable

Support sb, sh, lb, lh using byte enable
instead of non-word aligned reads and writes.

test: add cpu testbenches for c programs

test: add ram test

chore: add makefile for both verilog and c

feat: implement sb, sh, lb, lh support via masking

test: add simple cpu test

test: add basic testbenches
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