~ruther/verilog-riscv-semestral-project

ref: a400aceb574400fad6b269927793a5c13aab647c verilog-riscv-semestral-project/.gitignore -rwxr-xr-x 90 bytes
057ee98b — Rutherther 2 years ago 
chore: add generated bin, obj gitignore files
65ab00a4 — Rutherther 2 years ago 
chore: ignore obj_dir, vcd outputs
9c81ece2 — Rutherther 2 years ago 
chore: add gitignore