~ruther/verilog-riscv-semestral-project

ref: 9f4ac4dc09c9ccb93c6b1d9726bc7543ff09de00 verilog-riscv-semestral-project/src/cpu.sv -rwxr-xr-x 3.7 KiB 
fix: jump according to zero flag, not LSB zero!!

feat: implement sb, sh, lb, lh support via masking

fix: remove duplicit instruction and pc in cpu

refactor: move memory out of cpu

The cpu will have external memory,
that will allow for better testing
capabilities, and also makes more
sense.

feat: add cpu top level entity
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