~ruther/verilog-riscv-semestral-project: src/cpu_types.sv 938d89a274f0e1a4c50cc75857cffaa30e2d6f68

~ruther/verilog-riscv-semestral-project

ref: 938d89a274f0e1a4c50cc75857cffaa30e2d6f68 verilog-riscv-semestral-project/src/cpu_types.sv -rwxr-xr-x 291 bytes

b7fa590c — Rutherther 1 year, 7 months ago

chore: add cpu types for various sources

Better orientation by name instead of
number