refactor: save pc + 4 in stages

fix: jumping should flush two registers

feat: move jumping to execute stage

fix: temporarily turn off switching fetch valid

The instruction is always valid, since
for now jumps are calculated right away,
not one cycle after decode. That means
that next instruction is not fetched!

This is fine for simulation,
but when synthesized I think this
would slow down the processor as there
has to be the register file read performed
along with alu operation in one cycle.

First this should be changed, then uncomment
this line, to make the fetched pc+4 instruction
invalid when jumping.

Merge pull request #1 from Rutherther/feat/pipeline

Implement pipeline

docs: better document the stage code, organize it better

feat: implement pipeline