~ruther/verilog-riscv-semestral-project

ref: 914e69e6c0df1f4e3f33718891c838e42fe535b1 verilog-riscv-semestral-project/src/ram.sv -rwxr-xr-x 1.1 KiB 
chore: extend memory

tests: add register dump, printing

feat: add support for loading and saving ram from disk

feat: make RAM word aligned, add byte_enable

Support sb, sh, lb, lh using byte enable
instead of non-word aligned reads and writes.

fix: offset ram by bytes, not bits

feat: implement sb, sh, lb, lh support via masking

feat: add basic ram, alu, and register file
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