~ruther/verilog-riscv-semestral-project

ref: 89e944c05b3c054fee5be670cd1b00e0e487819b verilog-riscv-semestral-project/src/stages/decode.sv -rw-r--r-- 2.9 KiB 
feat: move jumping to execute stage

Merge pull request #1 from Rutherther/feat/pipeline

Implement pipeline
docs: better document the stage code, organize it better

feat: add forwarding signal for better debugging

feat: implement pipeline