~ruther/verilog-riscv-semestral-project

ref: 79c7be5c1c8ae2aea07f48d32abca650d24e8045 verilog-riscv-semestral-project/src/file_program_memory.sv -rw-r--r-- 319 bytes
chore: remove unnecessary executable flags

Closes #4.
tests: add register dump, printing
feat: add support for official tests
feat: pass program to execute by parameter
refactor: change program mem to file prog mem
feat: add program memory
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