~ruther/verilog-riscv-semestral-project

ref: 79c7be5c1c8ae2aea07f48d32abca650d24e8045 verilog-riscv-semestral-project/src/cpu_types.sv -rw-r--r-- 1.8 KiB 
chore: remove unnecessary executable flags

Closes #4.

refactor: save pc + 4 in stages

chore: clearer naming

feat: move jumping to execute stage

Merge pull request #1 from Rutherther/feat/pipeline

Implement pipeline
feat: implement pipeline

feat: implement sb, sh, lb, lh support via masking

chore: add cpu types for various sources

Better orientation by name instead of
number
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