~ruther/verilog-riscv-semestral-project: src/cpu_types.sv 773f4b9934627d8574aa6537bf7f289477336fe7

~ruther/verilog-riscv-semestral-project

ref: 773f4b9934627d8574aa6537bf7f289477336fe7 verilog-riscv-semestral-project/src/cpu_types.sv -rwxr-xr-x 291 bytes

b7fa590c — Rutherther 1 year, 7 months ago

chore: add cpu types for various sources

Better orientation by name instead of
number