~ruther/verilog-riscv-semestral-project (773f4b9934627d8574aa6537bf7f289477336fe7): / - ditigal.xyz git

~ruther/verilog-riscv-semestral-project

773f4b99 — Rutherther test: add simple cpu test 1 year, 7 months ago

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.envrc

10 bytes

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.gitignore

52 bytes

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flake.lock

1.5 KiB

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flake.nix

1.1 KiB

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src/

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testbench/

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