~ruther/verilog-riscv-semestral-project

ref: 6da6eb9e4ee2ac5f96d5bed40c4c46d57a64c79f verilog-riscv-semestral-project/tests/run.py -rwxr-xr-x 6.5 KiB
docs: add basic documentation
tests: add more custom tests
tests: add register dump, printing
tests: compile only once, copy proram, memory files to correct locations
feat: add support for official tests
tests: add python test environment for custom tests
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