~ruther/verilog-riscv-semestral-project

ref: b0f8702877121832dfdee7d921af417237673284 verilog-riscv-semestral-project/tests/run.py -rwxr-xr-x 6.5 KiB 
docs: add basic documentation

tests: add more custom tests

tests: add register dump, printing

tests: compile only once, copy proram, memory files to correct locations

feat: add support for official tests

tests: add python test environment for custom tests
Do not follow this link