~ruther/verilog-riscv-semestral-project

ref: 6ce1c83859b56b514f0a4536ddb388cacc77773e verilog-riscv-semestral-project/testbench d---------
707b5bfc — Rutherther 2 years ago
chore: add makefile for both verilog and c
acf0f724 — Rutherther 2 years ago
feat: implement sb, sh, lb, lh support via masking
773f4b99 — Rutherther 2 years ago
test: add simple cpu test
2929a779 — Rutherther 2 years ago
test: add basic testbenches