~ruther/verilog-riscv-semestral-project

ref: 6ce1c83859b56b514f0a4536ddb388cacc77773e verilog-riscv-semestral-project/Makefile -rwxr-xr-x 1.4 KiB
707b5bfc — Rutherther 2 years ago 
chore: add makefile for both verilog and c