~ruther/verilog-riscv-semestral-project: programs/start.S 5fe030988a21d47dd13af35a9b8697b2181cb6b7

~ruther/verilog-riscv-semestral-project

ref: 5fe030988a21d47dd13af35a9b8697b2181cb6b7 verilog-riscv-semestral-project/programs/start.S -rwxr-xr-x 95 bytes

a400aceb — Rutherther 1 year, 5 months ago

feat: make RAM word aligned, add byte_enable

Support sb, sh, lb, lh using byte enable
instead of non-word aligned reads and writes.

30a7f949 — Rutherther 1 year, 5 months ago

feat: add basic testing programs