~ruther/verilog-riscv-semestral-project

ref: 5fe030988a21d47dd13af35a9b8697b2181cb6b7 verilog-riscv-semestral-project/programs d--------- 
feat: make RAM word aligned, add byte_enable

Support sb, sh, lb, lh using byte enable
instead of non-word aligned reads and writes.

feat: add gcd program for testing

feat: add branches.c test

chore: remove gcc generated file

feat: add basic testing programs
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