~ruther/verilog-riscv-semestral-project

ref: 586cf7122913dbe1faece5e92b9da4bfc0d36403 verilog-riscv-semestral-project/src/cpu_types.sv -rwxr-xr-x 1.8 KiB 
chore: clearer naming

feat: move jumping to execute stage

Merge pull request #1 from Rutherther/feat/pipeline

Implement pipeline
feat: implement pipeline

feat: implement sb, sh, lb, lh support via masking

chore: add cpu types for various sources

Better orientation by name instead of
number
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