~ruther/verilog-riscv-semestral-project: src 51a684d98d8d4e7e256565e1ad0ec13a72116fd8

~ruther/verilog-riscv-semestral-project

ref: 51a684d98d8d4e7e256565e1ad0ec13a72116fd8 verilog-riscv-semestral-project/src d---------

51a684d9 — Rutherther 2 years ago

chore: formatting

8adc02d7 — Rutherther 2 years ago

feat: add basic ram, alu, and register file