~ruther/verilog-riscv-semestral-project

ref: 51842d387ac593fdcad90d2ed22e258a1c6780ee verilog-riscv-semestral-project/testbench d---------
feat: add support for official tests
feat: add support for loading and saving ram from disk
feat: pass program to execute by parameter
c682cc06 — Rutherther 2 years ago
feat: implement ebreak

Breaks the processor, can
exit the testcase
a400aceb — Rutherther 2 years ago
feat: make RAM word aligned, add byte_enable

Support sb, sh, lb, lh using byte enable
instead of non-word aligned reads and writes.
e7b5d989 — Rutherther 2 years ago
test: add cpu testbenches for c programs
0a9a14b7 — Rutherther 2 years ago
test: add ram test
707b5bfc — Rutherther 2 years ago
chore: add makefile for both verilog and c
acf0f724 — Rutherther 2 years ago
feat: implement sb, sh, lb, lh support via masking
773f4b99 — Rutherther 2 years ago
test: add simple cpu test
2929a779 — Rutherther 2 years ago
test: add basic testbenches