~ruther/verilog-riscv-semestral-project

ref: 38e84297e0e6abf0ec14d91878d5210792b801bd verilog-riscv-semestral-project/src/file_program_memory.sv -rwxr-xr-x 319 bytes 
feat: add support for official tests

feat: pass program to execute by parameter

refactor: change program mem to file prog mem

feat: add program memory
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