~ruther/verilog-riscv-semestral-project

ref: 34b74f067674498d19ea3797dfaa3330ce1514f0 verilog-riscv-semestral-project/src/control_unit.sv -rwxr-xr-x 3.2 KiB
feat: implement ebreak

Breaks the processor, can
exit the testcase
feat: implement sb, sh, lb, lh support via masking
fix: make sure alu is zeroed on memory load, write, jump
fix: force alu operation to addition for storing memory and pc
fix: propagate conditional jump from control_unit
feat: add control_unit wrapper over instruction_decoder
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