~ruther/verilog-riscv-semestral-project

ref: 32ebeea65b555fea871d5d5f91c13b27efcc6e57 verilog-riscv-semestral-project/src/register_file.sv -rwxr-xr-x 824 bytes
24eccbe0 — Rutherther 2 years ago 
refactor: parametrize register file
69ced879 — Rutherther 2 years ago 
fix: make rd1, rd2 in register_file regs
51a684d9 — Rutherther 2 years ago 
chore: formatting
8adc02d7 — Rutherther 2 years ago 
feat: add basic ram, alu, and register file