~ruther/verilog-riscv-semestral-project: src/ram.sv 30a7f9492e5e15f2d64dded11bc5080af6b54ec5

~ruther/verilog-riscv-semestral-project

ref: 30a7f9492e5e15f2d64dded11bc5080af6b54ec5 verilog-riscv-semestral-project/src/ram.sv -rwxr-xr-x 476 bytes

acf0f724 — Rutherther 2 years ago

feat: implement sb, sh, lb, lh support via masking

8adc02d7 — Rutherther 2 years ago

feat: add basic ram, alu, and register file