~ruther/verilog-riscv-semestral-project: src/ram.sv acf0f7243e7b45dc7db8e51c5c7ae659f7ef2bb3

~ruther/verilog-riscv-semestral-project

ref: acf0f7243e7b45dc7db8e51c5c7ae659f7ef2bb3 verilog-riscv-semestral-project/src/ram.sv -rwxr-xr-x 476 bytes

acf0f724 — Rutherther 1 year, 5 months ago

feat: implement sb, sh, lb, lh support via masking

8adc02d7 — Rutherther 1 year, 5 months ago

feat: add basic ram, alu, and register file