~ruther/verilog-riscv-semestral-project: src/control_unit.sv 2929a779a9d6e451c15f91ac7124f4081e2a04b4

~ruther/verilog-riscv-semestral-project

ref: 2929a779a9d6e451c15f91ac7124f4081e2a04b4 verilog-riscv-semestral-project/src/control_unit.sv -rwxr-xr-x 2.5 KiB

e44bfc9e — Rutherther 2 years ago

fix: propagate conditional jump from control_unit

52b05e5d — Rutherther 2 years ago

feat: add control_unit wrapper over instruction_decoder