~ruther/verilog-riscv-semestral-project: src/control_unit.sv e44bfc9ea42a45f5776158e8e51c025f185b4f56

~ruther/verilog-riscv-semestral-project

ref: e44bfc9ea42a45f5776158e8e51c025f185b4f56 verilog-riscv-semestral-project/src/control_unit.sv -rwxr-xr-x 2.5 KiB

e44bfc9e — Rutherther 1 year, 5 months ago

fix: propagate conditional jump from control_unit

52b05e5d — Rutherther 1 year, 5 months ago

feat: add control_unit wrapper over instruction_decoder