~ruther/verilog-riscv-semestral-project

ref: 1d7c9233527974f1bfd8db7e0027d5871911b997 verilog-riscv-semestral-project/programs/start.S -rwxr-xr-x 94 bytes 
chore: move inital sp to 1020

feat: make RAM word aligned, add byte_enable

Support sb, sh, lb, lh using byte enable
instead of non-word aligned reads and writes.

feat: add basic testing programs
Do not follow this link