~ruther/verilog-riscv-semestral-project

ref: 0d5d1a1fc04a21df2c7cf81ce969e9c02c125901 verilog-riscv-semestral-project/tests d---------
66d14163 — Rutherther 2 years ago
feat: move jumping to execute stage
f8e4e3ed — Rutherther 2 years ago
Merge pull request #1 from Rutherther/feat/pipeline

Implement pipeline
a6f4c7fc — Rutherther 2 years ago
chore: add new files to compilation list
b0f87028 — Rutherther 2 years ago
docs: add basic documentation
a079c57b — Rutherther 2 years ago
tests: add more custom tests
308a1462 — Rutherther 2 years ago
tests: add register dump, printing
18eeb2c5 — Rutherther 2 years ago
tests: compile only once, copy proram, memory files to correct locations
51842d38 — Rutherther 2 years ago
feat: add support for official tests
34b74f06 — Rutherther 2 years ago
tests: add python test environment for custom tests