~ruther/verilog-riscv-semestral-project: programs 0a9a14b7e6d78454c80c2331b0bd0150bc18d631

~ruther/verilog-riscv-semestral-project

ref: 0a9a14b7e6d78454c80c2331b0bd0150bc18d631 verilog-riscv-semestral-project/programs d---------

6ce1c838 — Rutherther 2 years ago

chore: remove gcc generated file

30a7f949 — Rutherther 2 years ago

feat: add basic testing programs