~ruther/verilog-riscv-semestral-project: .gitignore 0a9a14b7e6d78454c80c2331b0bd0150bc18d631

~ruther/verilog-riscv-semestral-project

ref: 0a9a14b7e6d78454c80c2331b0bd0150bc18d631 verilog-riscv-semestral-project/.gitignore -rwxr-xr-x 90 bytes

057ee98b — Rutherther 2 years ago

chore: add generated bin, obj gitignore files

65ab00a4 — Rutherther 2 years ago

chore: ignore obj_dir, vcd outputs

9c81ece2 — Rutherther 2 years ago

chore: add gitignore