~ruther/verilog-riscv-semestral-project: programs 057ee98bbecfb8a284b67bef50b04b70ae18e220

~ruther/verilog-riscv-semestral-project

ref: 057ee98bbecfb8a284b67bef50b04b70ae18e220 verilog-riscv-semestral-project/programs d---------

6ce1c838 — Rutherther 3 years ago

chore: remove gcc generated file

30a7f949 — Rutherther 3 years ago

feat: add basic testing programs