~ruther/verilog-riscv-semestral-project: src/instruction_decoder.sv 02405eecab38bfa1d85e88d908b52a589ee53d30

~ruther/verilog-riscv-semestral-project

ref: 02405eecab38bfa1d85e88d908b52a589ee53d30 verilog-riscv-semestral-project/src/instruction_decoder.sv -rwxr-xr-x 6.7 KiB

27fcb8d9 — Rutherther 1 year, 7 months ago

fix: do not use immediate in alu src for SB

32ebeea6 — Rutherther 1 year, 7 months ago

feat(decoder): implement memory mask, conditional jumps

e3c95ad3 — Rutherther 1 year, 7 months ago

feat: add instruction decoder