~ruther/verilog-riscv-semestral-project

ref: 02405eecab38bfa1d85e88d908b52a589ee53d30 verilog-riscv-semestral-project/src/instruction_decoder.sv -rwxr-xr-x 6.7 KiB
fix: do not use immediate in alu src for SB
feat(decoder): implement memory mask, conditional jumps
feat: add instruction decoder
Do not follow this link