~ruther/verilog-riscv-semestral-project

ref: cc87c7b82949ca7374bdb56b33b7bdbdfb9e8d5c verilog-riscv-semestral-project/.gitignore -rwxr-xr-x 52 bytes
cc87c7b8 — Rutherther fix(Makefile): make objdump and all testbenches work 2 years ago 
                                                                                
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.DS_Store
.idea
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.direnv/
obj_dir/
*.vcd