~ruther/vhdl-spi-2

ref: abfea28a8a2555ec22557089a359b3f2b6fd5f23 vhdl-spi-2/hdl_spi/.gitignore -rw-r--r-- 94 bytes
abfea28a — Rutherther fix: clock polarity on csn falling and rising. Proper wait after csn falling and before csn rising 11 months ago 
                                                                                
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modelsim.ini
sim_build/
__pycache__/
transcript
vsim.wlf
vsim_stacktrace.vstf
core
results.xml