fix: clkgen for various phases and polarities

feat: add tests for clock phase, polarity

fix: support other divisors than 2

fix: multiple issues in design

- setting lost rx data at correct time
- clearing lost rx data on start so the value is determined
- resolving pulses on stuff that depended on zero signal in ctrl
- allowing next tx right after one ended (crucial for divisor = 2)

feat: tests for multiple transmissions, rx lost

chore: add ghdl support vhdl2008 arg

chore: update cocotb

fix: sck generation

Sampling and changing was offset by one clock,
which is unnecesary. The clock wasn't correct
frequency, ie. divisor 2 led to division by 3

fix: master_ctrl_rst_n shou be used, not master_ctrl_rst, start_clock is split

fix: do not pass rx_serial_o from spi_multiplexor when not enabled

fix: prevent slave ctrl sending X's

feat: add first basic test

chore: few updates

feat: implement masterslave spi switch peripheral

feat: implement initial hdl_spi

feat(stm spi): add stm spi project

The spi slave project that will receive numbers over spi