4 files changed, 8 insertions(+), 10 deletions(-)

M hdl_spi/.gitignore
M hdl_spi/manifest.scm
M hdl_spi/tests/Makefile
D hdl_spi/tests/results.xml

@@ 4,4 4,5 @@ __pycache__/
 transcript
 vsim.wlf
 vsim_stacktrace.vstf
-core>
\ No newline at end of file
+core
+results.xml<
\ No newline at end of file

@@ 58,4 58,7 @@ testbenches in Python.")
     "python-pytest"
     "python"
     "vhdl-ls"
-    "make"))))
+    "make"
+
+    ;; "ghdl"
+    "gtkwave"))))

@@ 6,12 6,12 @@ TOPLEVEL_LANG ?= vhdl
 
 SRC = $(PWD)/../src
 
-VHDL_SOURCES=$(SRC)/spi_pkg.vhd $(wildcard $(SRC)/*.vhd)
+VHDL_SOURCES=$(SRC)/spi_pkg.vhd $(SRC)/rs_latch.vhd $(SRC)/register.vhd $(SRC)/shift_register.vhd $(SRC)/spi_clkgen.vhd $(SRC)/spi_clkmon.vhd $(SRC)/spi_multiplexor.vhd $(SRC)/spi_slave_ctrl.vhd $(SRC)/spi_master_ctrl.vhd $(SRC)/spi_master.vhd $(SRC)/spi_masterslave.vhd $(SRC)/spi_peripheral.vhd
 
 VCOM_ARGS = -2008
 
 # TOPLEVEL is the name of the toplevel module in your Verilog or VHDL file
-TOPLEVEL = spi_master
+TOPLEVEL = spi_masterslave
 
 # MODULE is the basename of the Python test file
 MODULE = test

@@ 1,6 0,0 @@
-<testsuites name="results">
-  <testsuite name="all" package="all">
-    <property name="random_seed" value="1735055524" />
-    <testcase name="simple_test" classname="test" file="/home/ruther/doc/uni/master-2/first_semester/mam/sem/hdl_spi/tests/test.py" lineno="4" time="1.6984877586364746" sim_time_ns="1025.001" ratio_time="603.4785913457854" />
-  </testsuite>
-</testsuites>