~ruther/vhdl-spi-2

vhdl-spi-2/hdl_spi/tests/test_spi_masterslave.py -rw-r--r-- 18.4 KiB
abfea28a — Rutherther 11 months ago
fix: clock polarity on csn falling and rising. Proper wait after csn falling and before csn rising
88da1f91 — Rutherther 11 months ago
tests: fix _t meaning (tri state)
38088715 — Rutherther 11 months ago
fix: short last sck pulse on slower clock
6a6d53c9 — Rutherther 1 year, 1 day ago
feat: add test for max divisor (256)
8d761360 — Rutherther 1 year, 1 day ago
feat: implement spi model narrow sck check
b5bfa2eb — Rutherther 1 year, 2 days ago
fix: assumptions about synthesizable code
fcd7233f — Rutherther 1 year, 3 days ago
feat: add test for lsbfirst
064c8c00 — Rutherther 1 year, 3 days ago
chore: remove todo comments
54521aad — Rutherther 1 year, 3 days ago
feat: add csn pulse test and rx, tx disabling test
e70719e8 — Rutherther 1 year, 4 days ago
feat: add tests for rx blocking
9c617e84 — Rutherther 1 year, 4 days ago
chore: move spi models to separate file